The present disclosure is directed to a layout testing method and a wafer manufacturing method.
As semiconductor devices are reduced in size, the relative rate of process changes that occur during the manufacture of the semiconductor device increases. That is, process errors increase in a semiconductor integrated circuit as the degree of integration increases. As a result, the design of a semiconductor integrated circuit needs to consider the effects of process changes. In particular, since process changes affect the manufacturing yield of a semiconductor device, it is useful to predict, in the design stage, how electrical characteristics of the product will change based on process changes.
The design of a semiconductor device may be checked by Layout Versus Schematic verification. Layout Versus Schematic (LVS) is a class of electronic design automation (EDA) verification software that determines whether a particular integrated circuit layout corresponds to the original schematic or circuit diagram of the design. LVS checking software recognizes the drawn shapes of the layout that represent the electrical components of the circuit, as well as the connections between them. These drawn shapes of the layout may be referred to as a circuit view. This netlist is compared by the LVS software against a similar schematic or circuit diagram's netlist.
LVS checking involves following three steps:
1. Extraction: The software program imports a database file containing all the layers drawn to represent the circuit during layout, and runs the database through logic operations to determine the semiconductor components represented in the drawing by their layers of construction. It then examines the various drawn metal layers and to determine how each of these components connects to the others.2. Reduction: The software combines the extracted components into series and parallel combinations if possible and generates a netlist representation of the layout database. A similar reduction is performed on the “source” Schematic netlist.3. Comparison: The extracted layout netlist is then compared to the netlist taken from the circuit schematic. If the two netlists match, then the circuit passes the LVS check. At this point it is said to be “LVS clean”. (Mathematically, the layout and schematic netlists are compared by performing a graph isomorphism check to see if the netlists are equivalent.)In most cases the layout will not pass LVS the first time, requiring the layout engineer to examine the LVS software's reports and make changes to the layout. Typical errors encountered during LVS include:1. Shorts: Two or more wires that should not be connected together have been and must be separated.2. Opens: Wires or components that should be connected are left dangling or only partially connected. These must be connected properly to fix this.3. Component Mismatches: Components of an incorrect type have been used (e.g. a low Vt MOS device instead of a standard Vt MOS device).4. Missing Components: An expected component has been left out of the layout.5. Parameter Mismatch: Components in the netlist can contain properties. The LVS software can be configured to compare these properties to a desired tolerance. If this tolerance is not met, then the LVS run is deemed to have a Property Error. A parameter that is checked may not be an exact match, but may still pass if the LVS software tolerance allows it. For example: if a resistor in a schematic had resistance=1000 (ohms) and the extracted netlist had a matched resistor with resistance=997 (ohms) and the tolerance was set to 2%, then this device parameter would pass as 997 is within 2% of 1000.